use core::sync::atomic::Ordering;

use limine::smp::Cpu;
use smp::CPUS;

use crate::irq::{
    apic::{APIC_INIT, CALIBRATED_TIMER_INITIAL, LAPIC},
    irq::IDT,
};

pub mod gdt;
pub mod smp;

unsafe extern "C" fn ap_entry(smp_info: &Cpu) -> ! {
    CPUS.write().get(smp_info.lapic_id).load();
    IDT.load();

    while !APIC_INIT.load(Ordering::SeqCst) {}
    LAPIC.lock().enable();

    let timer_initial = CALIBRATED_TIMER_INITIAL.load(Ordering::SeqCst);
    LAPIC.lock().set_timer_initial(timer_initial);

    // syscall::init();

    // while !SCHEDULER_INIT.load(Ordering::SeqCst) {}
    // log::debug!("Application Processor {} started", smp_info.id);

    // while !START_SCHEDULE.load(Ordering::SeqCst) {}
    // x86_64::instructions::interrupts::enable();

    loop {
        x86_64::instructions::interrupts::enable_and_hlt();
    }
}
